|Port Type||Name||Width (bits)||Description|
This page provides detailed information about the SystemC TLM2 Fast Processor Model of the ARM Cortex-M1 core.
Processor IP owner is ARM Holdings.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.
Model downloadable (needs registration and to be logged in) in package armm.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.
Model Variant name: Cortex-M1
ARMM Processor Model
Usage of binary model under license governing simulator usage.
Note that for models of ARM CPUs the license includes the following terms:
Licensee is granted a non-exclusive, worldwide, non-transferable, revocable licence to:
If no source is being provided to the Licensee: use and copy only (no modifications rights are granted) the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
If source code is being provided to the Licensee: use, copy and modify the model for the sole purpose of designing, developing, analyzing, debugging, testing, verifying, validating and optimizing software which: (a) (i) is for ARM based systems; and (ii) does not incorporate the ARM Models or any part thereof; and (b) such ARM Models may not be used to emulate an ARM based system to run application software in a production or live environment.
In the case of any Licensee who is either or both an academic or educational institution the purposes shall be limited to internal use.
Except to the extent that such activity is permitted by applicable law, Licensee shall not reverse engineer, decompile, or disassemble this model. If this model was provided to Licensee in Europe, Licensee shall not reverse engineer, decompile or disassemble the Model for the purposes of error correction.
The License agreement does not entitle Licensee to manufacture in silicon any product based on this model.
The License agreement does not entitle Licensee to use this model for evaluating the validity of any ARM patent.
The License agreement does not entitle Licensee to use the model to emulate an ARM based system to run application software in a production or live environment.
Source of model available under separate Imperas Software License Agreement.
Performance Monitors are not implemented.
Debug Extension and related blocks are not implemented.
Models have been extensively tested by Imperas. ARM Cortex-M models have been successfully used by customers to simulate the Micrium uC/OS-II kernel and FreeRTOS.
The model is configured with 16 interrupts and 2 priority bits (use override_numInterrupts parameter to change the number of interrupts; the number of priority bits is fixed in this profile).
MPU is not present. Use parameter override_MPU_TYPE to enable it if required.
SysTick timer is present. Use parameter SysTickPresent to disable it if required.
Unprivileged/Privileged Extension is present. Use parameter unprivilegedExtension to disable it if required.
VTOR register is present. Use parameter VTORPresent to disable it if required.
TCMs are present (ITCM is 16384 bytes, DTCM is 16384 bytes). Use parameters override_ITCMSize and override_DTCMSize to set TCM sizes if required (note that these parameters specify size codes in CFGITCMSZE/CFGDTCMSZE format, not byte sizes).
When TCMs are present, bus ports called ITCM and DTCM are created so that TCM contents may be viewed or modified externally by connecting to these ports. Parameter useInternalTCMs specifies whether TCM memory is modeled internally or externally. If modeled externally, the TCMs must be implemented on a bus which is then connected to the TCM bus ports listed above.
Use parameter override_ACTLR to specify whether TCMs should be enabled or disabled at reset.
Many instruction behaviors are described in the ARM ARM as CONSTRAINED UNPREDICTABLE. This section describes how such situations are handled by this model.
Equal Target Registers:
Some instructions allow the specification of two target registers (for example, double-width SMULL, or some VMOV variants), and such instructions are CONSTRAINED UNPREDICTABLE if the same target register is specified in both positions. In this model, such instructions are treated as UNDEFINED.
Floating Point Load/Store Multiple Lists:
Instructions that load or store a list of floating point registers (e.g. VSTM, VLDM, VPUSH, VPOP) are CONSTRAINED UNPREDICTABLE if either the uppermost register in the specified range is greater than 32 or (for 64-bit registers) if more than 16 registers are specified. In this model, such instructions are treated as UNDEFINED.
If-Then (IT) Block Constraints:
Where the behavior of an instruction in an if-then (IT) block is described as CONSTRAINED UNPREDICTABLE, this model treats that instruction as UNDEFINED.
Use of R13:
Use of R13 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows R13 to be used like any other GPR.
Use of R15:
Use of R15 is described as CONSTRAINED UNPREDICTABLE in many circumstances. This model allows such use to be configured using the parameter "unpredictableR15" as follows:
Value "undefined": any reference to R15 in such a situation is treated as UNDEFINED;
Value "nop": any reference to R15 in such a situation causes the instruction to be treated as a NOP;
Value "raz_wi": any reference to R15 in such a situation causes the instruction to be treated as a RAZ/WI (that is, R15 is read as zero and write-ignored);
Value "execute": any reference to R15 in such a situation is executed using the current value of R15 on read, and writes to R15 are allowed.
Value "assert": any reference to R15 in such a situation causes the simulation to halt with an assertion message (allowing any such unpredictable uses to be easily identified).
In this variant, the default value of "unpredictableR15" is "execute".
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.
Full model specific documentation on the variant Cortex-M1 is available OVP_Model_Specific_Information_armm_Cortex-M1.pdf.
Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/armm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x28
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.
The Cortex-M1 SystemC TLM2 Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_armm_Cortex-M1.pdf.
Information on the Cortex-M1 OVP Fast Processor Model can also be found on other web sites::
www.ovpworld.org has the library pages http://www.ovpworld.org/library/wikka.php?wakka=CategoryProcessor
www.imperas.com has more information on the model library
http://www.ovpworld.org: Creating Instruction Accurate Processor models using the VMI API
http://www.ovpworld.org: VMI Memory Modeled Component (VMI MMC) API Reference Guide
http://www.ovpworld.org: OR1K Demo Video Presentation
http://www.ovpworld.org: Altera Nios II Bare Metal & Cyclone III Linux Booting Demo Video
Currently available Fast Processor Model Families.